Sep'17 — Present, Bayan Lepas, Penang, Malaysia • Developed a skilled engineering team, ensuring the timely and successful delivery of hardware validation. • I managed and delivered Design Verification activities with a team of over 50 engineers across three countries. This included directing the eforts of more than four leads and a host of senior engineers specializing in IP, Subsystem, and SoC [Complete silicon]. • In Post-Silicon Validation Demonstrated exceptional cross-site collaboration and analytical prowess, spearheading the team and technology for six of Intel’s latest groundbreaking products. • Developed a scalable ‘End-to-End Endurance Test’ which outperformed traditional Platform validation methods by detecting a higher number of bugs. • Achieved significant cost savings by revamping the BOM strategy validation, saving USD 200K, and optimizing lab utilization, saving an additional USD 400K. • Developed a Customer Usage Validation approach, disseminating insights across IoT product segments, which enhanced execution precision and expanded test coverage in Silicon Validation. • Developed Subsystem and SoC level validation plans from scratch, as well as Interoperability Testing with top storage device manufacturers like Samsung and Kioxia as end product validation. • At Intel, I have earned multiple Divisional Recognition Awards (DRA) for enabling SoC validation content for device segments, contributions to the UFS boot camp by the Emulation team, implementing executed per validation strategies, and for UFS 3.0 joint validation with Samsung and Toshiba. • Received a Group level Excellence Award for my work with the BEAT (Bug Escape Analysis Team) workgroup and its implementation at the Malaysia site level. Additionally, I have been honored with numerous Spontaneous Recognition Awards (SRA) from peers, partners, and stakeholders for key milestone achievements and the successful completion of critical tasks. Engineering Manager – Post-Silicon Validation, Mirafra technologies Sep'14 — Aug'17, Bengaluru (Bangalore), India • I played a key role in delivering Storage IP validation for three generations of Qualcomm MDM Chipsets and eight MSM chipsets, overseeing the process from test case planning to customer sample release. • I managed the complete post-silicon validation cycle, which included developing validation plans, conducting reviews, and performing functional validation on FPGA and later SoC. I have a strong track record in validating storage modules such as IPA, SD, eMMC, USB2, and USB. • I have mentored numerous entry-level and junior engineers, actively participated in team growth, and led mass hiring initiatives. I directed a 12-member engineering team, ranging from Trainee Engineer to Senior Member of Technical Staf (SMTS), and was a finalist for the ‘Best Manager’ Award. Staf Validation Engineer Applied Micro Circuits Corporation (AMCC) Feb'12 — Sep'14, Pune, India • Contributed to Industries' first-in ARM-64 bit-based Micro Server Project. My hands-on experience includes using IXIA for RDMA, Protocol Analyzers for SATA and USB, and conducting Functional Validation and Process- Voltage-Temperature (PVT) for SD Host Controller 3.0. • FPGA & Silicon Validation for RDMA (RoCE); Collaboratively worked and resolved many issues along with Design/Verification and Validation teams. Senior Storage Engineer SmartPlay Technologies Nov'10 — Feb'12, Bengaluru (Bangalore), India • Being a storage validation Engineer, worked on 3G mobile teams in SD/MMC/SDIO IP domains. Hands on with Lauterbach Trace32 for efficient debugging and executions. • Resolved some complex issues in Media Playback found by the QA/FAEs and fixed it. Senior IP Validation Engineer Arasan Chip Systems Jul'05 — Oct'10, Thoothukudi, India • During this 5+ years tenure - have done IP validation using FPGA Hardware Development kit for Storage protocols on Windows and Linux x86 platforms. • Developed validation Framework, Test plan, Test case development and execution of SDHC (SD Host Controller) to latest SD 3.0 specification. • Worked on Bring-up for 10 Gbps Ethernet IP in FPGA for functionality and performance. • Worked on USB3.0 device mode bring up in FPGA. • Hands-on with Logic Analyzer, Oscilloscope, Ellisys USB3.0 Generator/Analyzer, LibUSB and iPerf/jPerf Lecturer at Lakshmi Ammal Polytechnic College Jan'05 — Jun'05, Kovilpatti, India • During this 6-month tenure worked as a lecturer in Computer Science Department and handled the subjects for Computer Science final year and pre-final year students. Also has handled subjects to Electrical & Electronics class students.